Project Proposal

Overview

DDRUM is a four-pad rhythm game in the spirit of DDR and Guitar Hero. Notes descend in four lanes on a display while a song plays. The player strikes one of four drum pads on the beat, and the system scores accuracy as Perfect, Good, or Miss with real-time visual feedback and a running score/combo.

The STM32L432 (Nucleo-L432KCU) acts as the central brain and system coordinator: it reads .wav files from an SD card, performs an offline FFT-based beat-detection analysis (using the CMSIS-DSP library) to auto-generate a beatmap, streams audio via I2S+DMA to a DAC, and drives the LED Matrix. The iCE40UP5K (UPduino v3.1) FPGA acts as a high-precision I/O accelerator: it captures drum pad hits with nanosecond accuracy, timestamps them, and stores them in a FIFO for the MCU to read. The result is a responsive, low-latency game that cleanly divides responsibilities: MCU for all logic, audio, and graphics; FPGA for time-critical hit detection. Success is defined as smooth 30+ FPS visuals on the Matrix, consistent audio-visual synchronization, accurate beat-detection on at least one song, consistent and accurate pad detection via the FPGA, and a real-time scoring system with a leaderboard. The design uses both the MCU and FPGA in roles beyond prior labs and introduces non-trivial new hardware: an I2S DAC, piezo sensor inputs, and an SD card reader.

Specifications

Audio Playback: .wav file playback via MCU DAC
Input Detection: Four piezo sensors captured by the FPGA with clear inputs
Visual Features: At least Four lanes, falling notes, combo counter, and live updates based on hits
Memory Reading: Reads music files, premade beatmaps, and reads/writes a persistent high-score leaderboard from an SD card using FatFs.
Synchronization: Smooth visuals, accurate scoring, synchronized audio, and a full playable song with consistent performance.
Reach Goal: Random Mode: 3 Game modes that vary on difficulty, selecting all bass notes randomly
Reach Goal: Audio Analysis: Successful beat-detection using FFT

Microcontroller Integration

The Nucleo-L432 provides the master clock (SysTick) for the entire system. It is responsible for all major logic. First, it implements a FAT file system (FatFs) to read .wav files from an SD card. In an “analysis” phase, it runs the CMSIS-DSP library’s FFT functions on the audio data to detect energy spikes in low/mid/high frequency bins, which it translates into a beatmap file (e.g., bass=pad1, snare=pad2) and saves back to the SD card. Second, during gameplay, it reads the .wav file again, streaming it via I2S and DMA to an external DAC for high-quality audio. Third, it simultaneously reads the generated beatmap and drives the game visuals (note highway, score) to an SPI LED Matrix display. Fourth, it implements a “survival mode” using the TRNG peripheral to generate an unpredictable note stream. Finally, it runs the game logic, reading hit timestamps from the FPGA’s FIFO over SPI and comparing them to the master clock to determine score (Perfect/Good/Miss). This combination of DSP libraries, I2S+DMA, TRNG, and FatFs is well beyond prior labs.

FPGA Integration

The iCE40UP5K is used as a high-speed, parallel I/O accelerator. Its sole task is to solve the problem of missed inputs. The four piezo drum pads (after passing through a simple comparator circuit) feed into the FPGA. The FPGA implements four high-precision timestamping modules in hardware. When a pad is hit, the FPGA captures the exact time of the rising edge (relative to its own clock) and stores this hit event (e.g., 4-bits for “lane” + 32-bits for “time”) into a hardware FIFO (First-In, First-Out) buffer. The MCU can then read from this FIFO over SPI at its own leisure (e.g., once per game loop). This design completely decouples the MCU’s main logic from the time-critical, nanosecond-precision task of input capture. This I/O co-processing, timestamping, and FIFO buffering is a new application of the FPGA.

I believe the beat-detection algorithm will be the riskiest element of our design; tuning the FFT and onset detection to create a “fun” and accurate beatmap from an arbitrary song is a significant DSP challenge.

Calculations

FFT Analysis. Using the CMSIS-DSP library, a 1024-point real FFT on the Cortex-M4 (with FPU) is highly optimized. Analyzing a full 3-minute, 44.1kHz song will be an “offline” process (e.g., 10-15 seconds) shown on a loading screen. Scroll mapping. At 30 FPS each frame advances by 33.3 ms. If we want a note to travel 240 px in 1500 ms, the scroll rate is $v = \frac{240}{1500} = \frac{0.16 px}{ms}$, so the per-frame step is $\Delta y \approx 5$ px. SPI bandwidth. Preloading a beatmap (~10-20 KB) is fast. Runtime traffic is minimal: the MCU just needs to send a “read” command to the FPGA’s FIFO over SPI, which can run at 8–12 MHz. Latency budget. Pad analog to digital logic < 100 µs; FPGA capture-to-FIFO < 1 µs. MCU SPI read to game logic < 100 µs. The end-to-end detection latency is well under 1 ms. The visual feedback is limited only by the LED Matrix’s refresh rate (33 ms). This leaves ample room for scoring windows at $\pm 35/ \pm 75$ ms. Power and levels. Logic runs at 3.3 V; I2S DAC and audio at 3.3 V or 5 V with a common ground.

Bill of Materials / Budget

Item	Part / ID	Qty	Source	Est. Price	Notes
FPGA board	UPduino v3.1 (iCE40UP5K)	1	Provided	$0.00
MCU board	Nucleo-L432KCU (STM32L432KC)	1	Provided	$0.00
Piezo discs (27–35 mm)	e.g., ABT-402-RP or generic	4		$4.00	Drum sensors ($1.00 each)
Comparator (optional)	LM393 or similar	2-4		$2.00	Signal conditioning for FPGA
AFE passives	10k/100k resistors, 100 nF caps (1%)	set	Stockroom	$0.00	Divider / RC
Momentary buttons	12 mm tactiles	3	Stockroom	$0.00	Start / Select / Pause
I2S DAC Module	MAX98357A or PCM5102	1		$7.00	Audio output (New)
microSD Card Module	e.g., Adafruit 254	1		$5.00	Music/Beatmap/Leaderboard (New)
LED Matrix Display	2.8” ILI9341 (320x240)	1		$15.00	Game Display (New)
Perfboard / wiring	—	—	Stockroom	$0.00	Interconnects
Enclosure materials	—	—	Makerspace	$0.00	Plywood + 3D printer filament

Subtotal (purchased items): $33.00

(This total is well within the $50 budget.)

Project Timeline — Weeks 8–15

Week	Date	Scheduled Topics	Deliverables	Project Milestone
8	Oct 13	Fall Break — No Class; Proposal Debriefs	Project Proposal	—
9	Oct 20	AES Lecture & FPGA Workshop	Lab 6	(A) MCU: Play audio from SD card via I2S+DMA. (S) FPGA: Implement piezo hit capture & FIFO.
10	Oct 27	Graphics, Displays, Motors & Speakers	Lab 7	(A) MCU: Drive LED Matrix display. Read hit timestamps from FPGA over SPI. (S) Integrate piezo-to-FPGA path.
11	Nov 3	Design Review Presentations (T/Th)	Design Review Presentation & Memo	Demo: Hitting a pad makes a sprite appear on the LED Matrix, while music plays.
12	Nov 10	Intro to RTOS; Direct Memory Access	—	Develop v1.0 of offline FFT beat-detection (CMSIS-DSP) on MCU.
13	Nov 17	Project Status Report & Demo; Connectors	Project Status Reports & Demo	Demo working game with auto-generated beatmap and scoring.
14	Nov 24	FFT Lecture; Thanksgiving — No Class (Th)	—	Implement Leaderboard. Implement TRNG random mode. Debugging/tuning.
15	Dec 4	Digital Signal Processing; Special Topics / Guest Lecture	Project Checkoffs, Report, Demo Day	Win or Die

Block Diagram

(The previous block diagram is no longer valid. This new architecture is as follows:)

Inputs: Four Piezo Sensors connect to the FPGA.
FPGA (I/O Accelerator): The FPGA’s Hit Detection + FIFO module communicates over SPI to the MCU.
MCU (The Brain):
- Reads/Writes to the SD Card Module (Fat32).
- Drives the SPI LED Matrix Display.
- Streams audio to the I2S DAC Module.
- Uses TRNG and CMSIS-DSP libraries.
Outputs: The I2S DAC outputs to a speaker/headphones. The LED Matrix displays the game.

Action Items

Finalize Audio Path (MCU side) – Implement SD card (FatFs) file reading and I2S+DMA streaming of .wav files to the DAC.
Develop Pad Detection (FPGA side) – Build piezo sensor circuit and implement FPGA hardware for hit timestamping and FIFO.
[S] Implement Beat-Detection (MCU side) – Integrate CMSIS-DSP library and develop an FFT-based algorithm to auto-generate beatmaps.
SPI Communication Protocol – Define and implement the simple “read from FIFO” SPI protocol.
Game Logic (MCU side) – Develop the game loop, scoring logic, and leaderboard system.
Graphics (MCU side) – Write drivers for the SPI LED Matrix to render the note highway, score, and hit flashes.
TRNG Mode – Use the TRNG peripheral to create a “survival” or “random” game mode.
Mechanical Integration – Assemble four-pad drum enclosure.
System Integration Test – Synchronize audio, visuals, and pad timing; validate scoring.
Final Debug and Polish – Tune FFT algorithm, scoring windows, and prepare final demo.

Task Division

Abe: MCU code (FFT/Beat-detection, game logic, scoring, TRNG mode), Mechanical design (drum pad housing)
Santiago: MCU code (I2S+DMA audio, SD Card/FatFs, SPI protocol, LED Matrix display driver), FPGA logic (Hit capture, timestamp, FIFO)
All Members: Debugging, documentation, and final presentation